PT7A4410 Datasheet, PDF (16/34 Pages) List of Unclassifed Manufacturers – T1/E1/OC3 System Synchronizer

Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Reset Circuit
Detailed Specifications
A simple power up reset circuit with about a 50µs reset active
(low) time is shown in Figure 14. Resistor R is for protection
P
only. The reset low time is not critical but should be greater
than 300ns.
Figure 14. Power-up Reset Circuit
PT7A4410/4410L
+5V
R
10kΩ
RST
R_P
1kΩ
C
10nF
Power Supply Decoupling
The PT7A4410/4410L has two V_CC pins and two GND pins.
Power decoupling capacitors should be included as shown in
Figure 15.
Figure 15. Power Supply Decoupling
Definitions of Critical Performance Specifictions
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the
synchronizing circuit. It is measured by applying a reference
signal with no jitter to the input of the device, and measuring
its output jitter. Intrinsic jitter may also be measured when the
device is in a non-synchronizing mode - such as free running
or holdover - by measuring the output jitter of the device.
Intrinsic jitter is usually measured with various band limiting
filters depending on the applicable standards.
Jitter Tolerance: Jitter tolerance is a measure of the ability of
a PLL to operate properly (i.e., remain in lock and/or regain
lock in the presence of large jitter magnitudes at various jitter
frequencies) when jitter is present on its reference. The appli-
cable standard specifies how much jitter to apply to the refer-
ence when testing for jitter tolerance.
Jitter Transfer: Jitter transfer or jitter attenuation refers to the
magnitude of jitter at the output of a device with respect to a
given amount of jitter at the input of the device. Input jitter is
applied at various amplitudes and frequencies, and output jit-
ter is measured with various filters depending on the appli-
cable standards.
C2
0.1µF
+
28
PT7A4410
/4410L
17 +
31
10
1 7+
C3
0.1µF
C1
0.1µF
Its 3 possible input frequencies and 9 outputs give the
PT7A4410/4410L 27 possible jitter transfer combinations.
However, only three cases of the jitter transfer specifications
are given in the AC Electrical Characteristics; as the remaining
combinations can be derived from them.
For the PT7A4410/4410L, two internal elements determine
the jitter attenuation. They are internal 1.9Hz low pass loop
filter and phase slope limiter. The phase slope limiter limits
the output phase slope to 5ns/125µs. Therefore, if the input
signal exceeds this rate, such as for very large amplitude low
frequency input jitter, the maximum output phase slope will
be limited (i.e., attenuated) to 5ns/125µs.
It should be noted that 1UI at 1.544MHz (644ns) is not equal
to 1UI at 2.048MHz (488ns). A transfer value using different
input and output frequencies must be calculated in common
units (e.g., seconds) as shown in the following example.
Example : When the T1 input jitter is 20UI (T1 UI Units) and
the T1 to T1 jitter attenuation is 18dB, The T1 and E1 output
jitter can be calculated as follows:
PT0106(09/02)
16
Ver:0