PT7A4410 Datasheet, PDF (5/34 Pages) List of Unclassifed Manufacturers – T1/E1/OC3 System Synchronizer

Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Pin Description
Table 2. Pin Description
Pin
1, 23, 31
10
2
3
4
5
6
7, 28
8
9
11
12
13
14
15
16
17
18
19
20
21
22
24
Name
GND
AGND
TCK
TCLR
TRST
SEC
PRI
V_CC
OSCo
OSCi
F16
RSP
F0
TSP
F8
C1.5
AVDD
C3
C2
C4
C19
ACKi
ACKo
Type
Descr iption
Ground Digital Ground (0V)
Ground Analog Ground
I
I
I
I
I
Power
O
I
O
O
O
O
O
O
Power
O
O
O
O
I
O
Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is internally
pulled up to V .
CC
TIE circuit reset (TTL): A low level on this pin will reset the TIE circuit, re-aligning
the output signals with the input signal. TCLR must be active (low) for at least 300ns.
This pin is internally pulled down to GND.
Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by putting
it in the Test-Logic-Reset state. This pin is internally pulled down to GND.
Secondar y reference (TTL): One of two independent input reference signals, internally
pulled down to GND.
Pr imar y reference (TTL): The other independent reference signal, internally pulled
down to GND.
Power supply +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ
Oscillator master clock output (CMOS): Output of 20MHz master clock
Oscillator master clock input (CMOS): Input of 20MHz master clock (can be connected
directly to a clock source)
Fr ame pulse ST-BUS 16.384Mb/s (CMOS): 8kHz frame signal with 61ns low level pulse
that marks the beginning of a ST-BUS frame, typically used for ST-BUS opetation at
8.192Mb/s. See figure 18.
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the end of an ST-BUS frame. See Figure 19.
Fr ame pulse ST-BUS 2.048 Mb/s (CMOS): 8kHz frame signal with 244ns low level
pulse that marks the beginning of a ST-BUS frame e, typically used for ST-BUS opetation
at 2.048Mb/s. See figure 18.
Tr ansmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. See Figure 19.
Fr ame pulse ST-BUS 8.192 Mb/s (CMOS): 8kHz frame signal with 122ns high level
pulse that marks the beginning of a ST-BUS frame
1.544 MHz clock (CMOS): This output is used in T1 applications.
Analog Power Supply: +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ
3.088 MHz clock (CMOS): This output is used in T1 applications.
2.048 MHz clock (CMOS): This output is used for ST-BUS operation at 2.048Mb/s.
4.096 MHz clock (CMOS): This output is used for ST-BUS operation at 2.048Mb/s and
4.096Mb/s.
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS-3 applications.
Analog PLL Clock Input (CMOS Input). This input clock is a reference for an internal
analog PLL. This pin is internally pulled down to GND.
Analog PLL Clock Output (CMOS Output). This output clock is generated by the
internal analog PLL.
PT0106(09/02)
5
Ver:0