PT7A4410 Datasheet, PDF (24/34 Pages) List of Unclassifed Manufacturers – T1/E1/OC3 System Synchronizer

Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Table 14. Input and Output Timing (Continued)
Sym
Descr iption
Test Conditions*
Min
Typ
Max Units
t_C16WL C16 Pulse Width Low
26
t
TSPW
t_RSPW
TSP Pulse Width High
RSP Pulse Width High
478
1-14, 21
478
t_C19W
C19 Pulse Width High or Low
16
t
F0 Pulse Width Low
230
F0WL
t_F8WH
F8 Pulse Width High
111
t_F16WL
F16 Pulse Width Low
52
t
ORF
Output Clock and Frame Pulse Rising
or Falling Time
1-14, 21, 39
t_S
Input Controls Setup Time
100
t
Input Controls Hold Time
100
H
* Refer to the Test Conditions on Page 32 for details.
37
ns
494
ns
495
ns
36
ns
258
ns
133
ns
70
ns
9
ns
ns
ns
Figure 17. Input to Output Timing (Normal State, after TCLR or RST)
PRI/SEC
8kHz
PRI/SEC
1.544M Hz
PRI/SEC
2.048M Hz
t_RW
t_R15D
t_RW
t_R2D
t_RW
t_R8D
V_T
V
T
V_T
F8
V
T
Note: Input to output delay values are valid after a TCLR or RST with no further state changes.
PT0106(09/02)
24
Ver:0