VS1103B Datasheet, PDF (54/61 Pages) List of Unclassifed Manufacturers – MIDI/ADPCM AUDIO CODEC

VLSI
Solution ^y
VS1103b
VS1103B
8. VS1103B REGISTERS
8.12 Timers v1.0 2002-04-23
There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,
a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.
When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value
register, and continues downcounting. A timer stays in that loop as long as it is enabled.
A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding the
timer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer is
enabled (1) or disabled (0) by a corresponding bit of the enable register.
8.12.1 Registers
Reg
0xC030
0xC031
0xC034
0xC035
0xC036
0xC037
0xC038
0xC039
0xC03A
0xC03B
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Timer registers, prefix TIMER
Reset Abbrev
Description
0 CONFIG[7:0] Timer configuration
0 ENABLE[1:0] Timer enable
0 T0L
0 T0H
0 T0CNTL
0 T0CNTH
0 T1L
0 T1H
0 T1CNTL
0 T1CNTH
Timer0 startvalue - LSBs
Timer0 startvalue - MSBs
Timer0 counter - LSBs
Timer0 counter - MSBs
Timer1 startvalue - LSBs
Timer1 startvalue - MSBs
Timer1 counter - LSBs
Timer1 counter - MSBs
8.12.2 Configuration TIMER CONFIG
Name
TIMER CF CLKDIV
TIMER CONFIG Bits
Bits Description
7:0 Master clock divider
TIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clock
frequency
f_i
=
fm
c+1
,
where
f_m
is
the
master
clock
frequency
and
c
is
TIMER
CF
CLKDIV.
Example:
With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/sampling
clock
would
thus
be
f_i
=
12M Hz
3+1
=
3M Hz.
Version 1.01, 2007-09-03
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