VS1103B Datasheet, PDF (29/61 Pages) List of Unclassifed Manufacturers – MIDI/ADPCM AUDIO CODEC

VLSI
Solution ^y
VS1103b
VS1103B
6. FUNCTIONAL DESCRIPTION
2 _{In addition, the cycles spent in the user application routine must be counted.}
3 _{Firmware changes the value of this register immediately after reset to 0x38, and in less than 100 ms to}
0x30.
4 _{When mode register write specifies a software reset the worst-case time is 16600 XTALI cycles.}
5 _{Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not a}
good idea to send SCI or SDI bits while this register update is in progress.
Note: it is not allowed to do an SCI operation while DREQ is low. If this is done, however, DREQ stays
low even after the SCI operation has been processed.
6.6.1 SCI MODE (RW)
SCI MODE is used to control the operation of VS1103b and defaults to 0x0800 (SM SDINEW set).
Name
SM DIFF
SM RECORD PATH
SM RESET
SM OUTOFMIDI
SM PDOWN
SM TESTS
SM ICONF
SM DACT
SM SDIORD
SM SDISHARE
SM SDINEW
SM EARSPEAKER
SM LINE IN
SM ADPCM
Bit
0
1
2
3
4
5
7:6
8
9
10
11
13:12
14
15
SCI MODE bits
Function
Differential
Choose ADPCM recording
path
Soft reset
Cancel MIDI decoding
Powerdown
Allow SDI tests
Input configuration
DCLK active edge
SDI bit order
Share SPI chip select
VS1002 native SPI modes
Earspeaker setting
A/D stream input
selector
ADPCM recording active
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
0
1
0
1
0
1
0
1
0
1
2
3
0
1
0
1
Description
normal in-phase audio
left channel inverted
A/D stream
Mixer output
no reset
reset
no
yes
power on
powerdown
not allowed
allowed
SDI MIDI, SCI ADPCM
SCI MIDI, SDI ADPCM
UART RT-MIDI, SCI ADPCM
UART RT-MIDI, SDI ADPCM
rising
falling
MSb first
MSb last
no
yes
no
yes
off
low
mid
high
microphone
line in
no
yes
Version 1.01, 2007-09-03
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