VS1103B Datasheet, PDF (33/61 Pages) List of Unclassifed Manufacturers – MIDI/ADPCM AUDIO CODEC

VLSI
Solution ^y
VS1103b
VS1103B
6. FUNCTIONAL DESCRIPTION
Note:
Because
maximum
sample
rate
is
XT ALI
256
,
all
sample
rates
are
not
available
if
XTALI
<
12.288
MHz.
Example: If SCI CLOCKF is 0xC3E8, SC MULT = 6 and SC FREQ = 0x3E8 = 1000. This means that
XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to 4.0×XTALI = 48 MHz.
6.6.5 SCI DECODE TIME (RW)
When decoding correct MIDI data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. In that case the new value should be written twice.
SCI DECODE TIME is reset at every software reset and also when MIDI decoding starts or ends.
6.6.6 SCI AUDATA (RW)
The current sample rate and number of channels can be found in bits 15:1 and 0 of SCI AUDATA,
respectively. Bits 15:1 contain the sample rate divided by two, and bit 0 is 0 for mono data and 1 for
stereo. Writing to SCI AUDATA will change the sample rate directly (not recommended for VS1103b!).
As VS1103b always runs in stereo mode at 44100 Hz, contents of this register is always 0xAC45 (44101).
6.6.7 SCI WRAM (RW)
SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start
address must be initialized by writing to SCI WRAMADDR prior to the first write/read of SCI WRAM.
As 16 bits of data can be transferred with one SCI WRAM write/read, and the instruction word is 32 bits
long, two consecutive writes/reads are needed for each instruction word. The byte order is big-endian
(i.e. most significant byte first). After each full-word write/read, the internal pointer is autoincremented.
6.6.8 SCI WRAMADDR (W)
SCI WRAMADDR is used to set the program address for following SCI WRAM writes/reads. Address
offset of 0 is used for X, 0x4000 for Y, and 0x8000 for instruction memory. Peripheral registers can also
be accessed.
SM WRAMADDR
Start. . . End
0x1800. . . 0x187F
0x5800. . . 0x587F
0x8030. . . 0x84FF
0xC000. . . 0xFFFF
Dest. addr.
Start. . . End
0x1800. . . 0x187F
0x1800. . . 0x187F
0x0030. . . 0x04FF
0xC000. . . 0xFFFF
Bits/
Word
16
16
32
16
Description
X data RAM
Y data RAM
Instruction RAM
I/O
Version 1.01, 2007-09-03
33