VS1103B Datasheet, PDF (28/61 Pages) List of Unclassifed Manufacturers – MIDI/ADPCM AUDIO CODEC

VLSI
Solution ^y
VS1103b
VS1103B
6. FUNCTIONAL DESCRIPTION
6.4 Serial Data Interface (SDI)
The serial data interface is meant for transferring ADPCM or MIDI data.
If the input of the decoder is invalid or it is not received fast enough, analog outputs are automatically
muted.
Also several different tests may be activated through SDI as described in Chapter 7.
6.5 Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1103b is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
• control of the operation mode, clock, and builtin effects
• access to status information and header data
• access to encoded digital data
• uploading user programs
6.6 SCI Registers
SCI registers, prefix SCI
Reg Type Reset
Time¹ Abbrev[bits]
Description
0x0 rw 0x800
200 CLKI⁴ MODE
Mode control
0x1 rw 0x3C³
40 CLKI STATUS
Status of VS1103b
0x2 rw 0
2100 CLKI BASS
Built-in bass/treble enhancer
0x3 rw 0
11000 XTALI⁵ CLOCKF
Clock freq + multiplier
0x4 rw 0
40 CLKI DECODE TIME Stream 0 decode time
0x5 rw 0
3200 CLKI AUDATA
Misc. audio data
0x6 rw 0
80 CLKI WRAM
RAM write/read
0x7 rw 0
80 CLKI WRAMADDR Base address for RAM write/read
0x8 rw 0
90 CLKI IN0
Input 0
0x9 rw 0
90 CLKI IN1
Input 1
0xA rw 0
3200 CLKI² AIADDR
Start address of application
0xB rw 0
2100 CLKI VOL
Volume control
0xC rw 0
70 CLKI² MIXERVOL
Mixer volume
0xD rw 0
50 CLKI² ADPCMRECCTL IMA ADPCM record control
0xE rw 0
50 CLKI² AICTRL2
Application control register 2
0xF rw 0
50 CLKI² AICTRL3
Application control register 3
1 _{This is the worst-case time that DREQ stays low after writing to / reading from this register. The user}
may choose to skip the DREQ check for those register writes that take less than 100 clock cycles to
execute.
Version 1.01, 2007-09-03
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