LM3S608 Datasheet, PDF (53/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S608 Microcontroller
6.1.2.6
6.1.2.7
6.1.3
6.1.4
6.1.4.1
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 19-13 on page 394.
Low Drop-Out
A reset can be initiated when the internal low drop-out (LDO) regulator output goes unregulated.
This is initially disabled and may be enabled by software. LDO is controlled with the LDO Power
Control (LDOPCTL) register. The LDO reset sequence is as follows:
1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The LDO reset timing is shown in Figure 19-14 on page 394.
Power Control
The Stellaris^® microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the controller's internal logic. The LDO regulator provides software a mechanism
to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V
(inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the
LDO Power Control (LDOPCTL) register.
Clock Control
System control determines the control of clocks in this part.
Fundamental Clock Sources
There are two clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
October 01, 2007
53
Preliminary