LM3S608 Datasheet, PDF (226/416 Pages) List of Unclassifed Manufacturers – Microcontroller

Analog-to-Digital Converter (ADC)
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
11.4
Register Map
Table 11-2 on page 226 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 11-2. ADC Register Map
Offset Name
Type
0x000 ADCACTSS
0x004 ADCRIS
0x008 ADCIM
0x00C ADCISC
0x010 ADCOSTAT
0x014 ADCEMUX
0x018 ADCUSTAT
0x020 ADCSSPRI
0x028 ADCPSSI
0x030 ADCSAC
0x040 ADCSSMUX0
0x044 ADCSSCTL0
0x048 ADCSSFIFO0
0x04C ADCSSFSTAT0
0x060 ADCSSMUX1
0x064 ADCSSCTL1
0x068 ADCSSFIFO1
0x06C ADCSSFSTAT1
0x080 ADCSSMUX2
0x084 ADCSSCTL2
0x088 ADCSSFIFO2
0x08C ADCSSFSTAT2
0x0A0 ADCSSMUX3
R/W
RO
R/W
R/W1C
R/W1C
R/W
R/W1C
R/W
WO
R/W
R/W
R/W
RO
RO
R/W
R/W
RO
RO
R/W
R/W
RO
RO
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.3210
-
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0100
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0100
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0100
0x0000.0000
Description
ADC Active Sample Sequencer
ADC Raw Interrupt Status
ADC Interrupt Mask
ADC Interrupt Status and Clear
ADC Overflow Status
ADC Event Multiplexer Select
ADC Underflow Status
ADC Sample Sequencer Priority
ADC Processor Sample Sequence Initiate
ADC Sample Averaging Control
ADC Sample Sequence Input Multiplexer Select 0
ADC Sample Sequence Control 0
ADC Sample Sequence Result FIFO 0
ADC Sample Sequence FIFO 0 Status
ADC Sample Sequence Input Multiplexer Select 1
ADC Sample Sequence Control 1
ADC Sample Sequence Result FIFO 1
ADC Sample Sequence FIFO 1 Status
ADC Sample Sequence Input Multiplexer Select 2
ADC Sample Sequence Control 2
ADC Sample Sequence Result FIFO 2
ADC Sample Sequence FIFO 2 Status
ADC Sample Sequence Input Multiplexer Select 3
See
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October 01, 2007
Preliminary