LM3S608 Datasheet, PDF (199/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S608 Microcontroller
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4
Register Map
Table 10-1 on page 199 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
Offset Name
Type
Reset
Description
0x000 WDTLOAD
0x004 WDTVALUE
0x008 WDTCTL
0x00C WDTICR
0x010 WDTRIS
0x014 WDTMIS
0x418 WDTTEST
0xC00 WDTLOCK
R/W
0xFFFF.FFFF Watchdog Load
RO
0xFFFF.FFFF Watchdog Value
R/W
0x0000.0000 Watchdog Control
WO
-
Watchdog Interrupt Clear
RO
0x0000.0000 Watchdog Raw Interrupt Status
RO
0x0000.0000 Watchdog Masked Interrupt Status
R/W
0x0000.0000 Watchdog Test
R/W
0x0000.0000 Watchdog Lock
See
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October 01, 2007
199
Preliminary