LM3S608 Datasheet, PDF (49/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S608 Microcontroller
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
... I
N
O
U
T
O
E
I
N
I
N
O
U
T
O
E
... I
N
O
U
T
O TDO
E
GPIO PB6
GPIO m
RST
GPIO m+1
GPIO n
5.4.2.4
5.4.2.5
5.4.2.6
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris^® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
October 01, 2007
49
Preliminary