LM3S316 Datasheet, PDF (40/421 Pages) List of Unclassifed Manufacturers – Microcontroller

ARM Cortex-M3 Processor Core
Register 1: SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features.
SysTick Control and Status
Address: 0xE000E010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COUNTFLAG
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
RO
RO
RO
Reset
0
0
0
reserved
CLKSOURCE TICKINT ENABLE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
Name
reserved
Type
RO
16
COUNTFLAG R/W
15:3
reserved
RO
2
CLKSOURCE R/W
1
TICKINT
R/W
0
ENABLE
R/W
Reset
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
Returns 1 if timer counted to 0 since last time this was read.
Clears on read by application. If read by the debugger using the
DAP, this bit is cleared on read-only if the MasterType bit in the
AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
Reserved bits return an indeterminate value, and should never
be changed.
0 = external reference clock. (Not implemented for Stellaris
microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the
same time as the core clock. The core clock must be at least 2.5
times faster than the reference clock. If it is not, the count values
are Unpredictable.
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler.
Software can use the COUNTFLAG to determine if ever counted
to 0.
1 = counter operates in a multi-shot way. That is, counter loads
with the Reload value and then begins counting down. On
reaching 0, it sets the COUNTFLAG to 1 and optionally pends
the SysTick handler, based on TICKINT. It then loads the Reload
value again, and begins counting.
0 = counter disabled.
40
April 27, 2007
Preliminary