LM3S316 Datasheet, PDF (135/421 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S316 Data Sheet
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing a DRV2 bit for a
GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the
GPIODR8R register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
Offset 0x500
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV2
Type
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit/Field
31:8
7:0
Name
reserved
DRV2
Type
RO
R/W
Reset
0
0xFF
Description
Reserved bits return an indeterminate value, and should never
be changed.
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the
second clock cycle after the write.
April 27, 2007
135
Preliminary