LM3S316 Datasheet, PDF (37/421 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S316 Data Sheet
2.2.2
2.2.3
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is
similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
Debug
ATB
Slave
Port
ATB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
APB
Slave
Port
APB
Interface
2.2.4
2.2.5
2.2.6
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S316 controller and supports the
standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full
support for protection regions, overlapping protection regions, access permissions, and exporting
memory attributes to the system.
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
„ Facilitates low-latency exception and interrupt handling
„ Controls power management
„ Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
April 27, 2007
37
Preliminary