LM3S316 Datasheet, PDF (168/421 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TAAMS TACMR
TAMR
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1:0
Name
reserved
TAAMS
TACMR
TAMR
Type
RO
R/W
R/W
R/W
Reset
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerA Alternate Mode Select
0: Capture mode is enabled.
1: PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
GPTM TimerA Capture Mode
0: Edge-Count mode.
1: Edge-Time mode.
GPTM TimerA Mode
0x0: Reserved.
0x1: One-Shot Timer mode.
0x2: Periodic Timer mode.
0x3: Capture mode.
The Timer mode is based on the timer configuration defined by
bits 2:0 in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer
modes for TimerA.
In 32-bit timer configuration, this register controls the mode and
the contents of GPTMTBMR are ignored.
168
April 27, 2007
Preliminary