HMS38112 Datasheet, PDF (37/73 Pages) List of Unclassifed Manufacturers – 4-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 3. Architecture
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of f_OSC/48 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
Ø Ø The overflow time is 8 6 2¹³/f_OSC (108.026ms at f_OSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to STOP Operation>)
f_OSC/48
Reset
by instruction
Power-On Reset
Low VDD Detection
Binary counter(14 steps)
RESET (edge-trigger)
CPU reset
Fig 3-6 Block Diagram of Watch-dog Timer
3-9