HMS38112 Datasheet, PDF (35/73 Pages) List of Unclassifed Manufacturers – 4-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 3. Architecture
Reset Operation
HMS38112/39112 have three reset sources. One is a built-in Power-on reset circuit, another
is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer
(WDT). All reset operations are internal in the HMS38112.
Built-in Power On Reset Circuit
Ð^{HMS38112/39112 has a built-in Power-on reset circuit consisting of an about}
1 Resistor and a 3pF Capacitor. When the Power-on reset pulse occurs,
system reset signal is latched and WDT is cleared. After the overflow time of WDT
(2¹³ x System clock time), system reset signal is released.
VDD
1Ð
3pF
GND
VCC
Counter
(WDT)
<HMS38/39XXX>
System
RESETB
System
RESETB
t_reset
About 108msec at
fosc = 3.64MHz
Fig. 3-4 Power-On Reset Circuit and Timing Chart
3-7