HMS38112 Datasheet, PDF (32/73 Pages) List of Unclassifed Manufacturers – 4-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 3. Architecture
Accumulator (A_CC)
The 4-bit register for holding data and calculation results.
Arithmetic and Logic Unit (ALU)
In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)
(1) Operation circuit (ALU) :
The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of A_CC (A_CC+1)
(2) Status logic :
This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or underflow
in operation and two inputs unequal.
State Counter (SC)
A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing sequentially.
Therefore, the next instruction is prefetched so that its execution is completed
within the fetch cycle.
T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6
Fetch cycle N
Execute cycle N
Execute cycle N-1
Fetch cycle N-1
é Phase
ê Phase
ë Phase
Machine
Cycle
Machine
Cycle
Fig. 3-3 Fundamental timing chart
3-4