OXFW911 Datasheet, PDF (12/32 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
6.2 1394 Link-Phy interface
The timings for 1394 Link – Phy are shown below :
Symbol Parameter
Min
tlsu Setup Time, PD[7:0] and CTL[1:0] before PhyClk
8
tlh Hold Time, PD[7:0] and CTL[1:0] after PhyClk
0
Tld1 Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0]
2
and Lreq outputs valid
Tld2 Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0],
2
CTL[1:0] and Lreq outputs valid
Tld3 Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs
2
invalid (high impedance)
tcyc Duty Cycle
45
Table 8: OXFW911 Link-Phy interface timings
OXFW911
Max
Units
ns
ns
10
ns
10
ns
10
ns
55
%
Data Sheet Rev 1.1
Page 12