OXFW911 Datasheet, PDF (11/32 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
OXFW911
Symbol Parameter
Mode 3 Mode 3 Mode 4 Mode4 Mode5 Mode5 Unit
min
max
min
max
min
max
s
t2cyctyp Typical sustained average two 100
60
40
ns
cycle time
tcyc Cycle time allowing for clock 39
25
20
ns
variations ( refer to ATA spec)
t2cyc Two cycle time allowing for clock
86
57
40
ns
variations ( refer to ATA spec )
tds Data setup time at recipient
7
5
4.0
ns
tdh Data hold time at recipient
5
5
4.6
ns
tdvs Data valid setup time at sender 20
6
4.8
ns
(from data bus being valid until
STROBE edge )
tdvh Data valid hold time at sender
6
6
4.8
ns
(from STROBE edge until data
may become invalid
tfs
First STROBE time (for device to
0
130
0
120
0
90
ns
first negate DSTROBE from
STOP during a data-in burst)
tli
Limited interlock time
0
100
0
100
0
75
ns
tmli Interlock time with minimum
20
20
20
ns
tui Unlimited interlock time
0
0
0
ns
taz Maximum time allowed for output
10
10
10
ns
drivers to release (from being
asserted or negated)
tzah Minimum delay time required for 20
20
20
ns
tzad output drivers to assert or negate
0
0
0
(from released state)
tenv Envelope time ( from DMACK# to
20
55
20
55
20
50
ns
STOP and HDMARDY# during
data-out burst initiation
trfs Ready-to-final-STROBE time ( no
60
60
50
ns
STROBE edges shall be sent this
long after the negation of
DDMARDY#
trp Ready-to-pause time ( time that 100
100
85
ns
recipient shall wait to initiate
pause after negating DMARDY# )
tiordyz Pull-up time before allowing
20
20
20
ns
IORDY to be released
tziordy Minimum time a device shall wait
0
0
0
ns
before driving IORDY
tack Setup and hold times for 20
20
20
ns
DMACK# (before assertion or
negation )
tss Time from STROBE edge to 50
50
50
ns
negation of DMARQ or assertion
of STOP (when sender terminates
a burst )
Table 7a: OXFW911 Ultra DMA timings (cont)
Data Sheet Rev 1.1
Page 11