OXFW911 Datasheet, PDF (10/32 Pages) List of Unclassifed Manufacturers – IEEE1394 to ATA/ATAPI Native Bridge

OXFORD SEMICONDUCTOR LTD.
OXFW911
Symbol Parameter
t2cyc
tcyc
t2cyc
tds
tdh
tdvs
tdvh
tfs
tli
tmli
tui
taz
tzah
tzad
tenv
tsr
trfs
trp
tiordyz
tziordy
tack
tss
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender (from
STROBE edge until data may
become invalid
First STROBE time (for device to
first negate DSTROBE from STOP
during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
STROBE to DMARDY time ( refer
to ATA spec
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long after the negation of
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate pause
after negating DMARDY# )
Pull-up time before allowing IORDY
to be released
Minimum time a device shall wait
before driving IORDY
Setup and hold times for DMACK#
(before assertion or negation )
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates a
burst )
Mode 0
min
240
112
230
15
5
70
6
0
0
20
0
20
0
20
160
0
20
50
Mode 0 Mode 1
max
min
160
75
156
10
5
48
6
230
0
150
0
20
0
10
20
0
70
20
50
75
125
20
0
20
50
Mode1
max
200
150
10
70
30
70
20
Mode 2
min
120
Mode 2
max
Units
ns
55
ns
117
ns
7
ns
5
ns
34
ns
6
ns
0
170
ns
0
150
ns
20
ns
0
ns
10
ns
20
ns
0
20
70
ns
20
ns
60
ns
100
ns
20
ns
0
ns
20
ns
50
ns
Table 7: OXFW911 Ultra DMA timings
Data Sheet Rev 1.1
Page 10