M13S128168A_08 Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-4
Min
Max
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE command
Row Cycle Time
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
ACTIVE to READ with
AUTOPRECHARGE command
ACTIVE bank A to ACTIVE bank B
command
Write recovery time
Write data in to READ command delay
Col. Address to Col. Address delay
Average periodic refresh interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup
time
Load Mode Register / Extended Mode
register cycle time
Exit self refresh to READ command
Exit self refresh to non-READ
command
Autoprecharge write
recovery+Precharge time
t_HP
t_QH
t_QHS
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RAP
t_RRD
t_WR
t_WTR
t_CCD
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_WPRES
t_MRD
t_XSRD
t_XSNR
t_DAL
t_CLmin or
t_CHmin
t_HP-t_QHS
-
40
52
60
15
15
18
10
15
2
1
-
0.25
0.4
0.9
0.4
0
2
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
-
-
0.5
70K
-
-
-
-
-
-
-
-
-
15.6
-
0.6
1.1
0.6
-
-
-
-
-
-5
Min
Max
t_CLmin or
t_CHmin
t_HP-t_QHS
-
-
-
0.45
40
70K
60
-
70
-
15
-
15
-
18
-
10
-
15
-
2
-
1
-
-
15.6
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
2
-
200
-
75
-
(t_WR/t_CK)
+
(t_RP/t_CK)
-6
Min
Max
t_CLmin or
t_CHmin
-
t_HP-t_QHS
-
-
0.5
42
70K
60
-
72
-
18
-
18
-
18
-
12
-
15
-
2
-
1
-
-
15.6
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
1
-
200
-
75
-
(t_WR/t_CK)
+
(t_RP/t_CK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
t_CK
us
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
ns
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
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