M13S128168A_08 Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
DDR SDRAM
Features
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z V_DD = 2.375V ~ 2.75V, V_DDQ = 2.375V ~ 2.75V
z V_DD = 2.6V ~ 2.8V, V_DDQ = 2.6V ~ 2.8V [for speed -4]
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z SSTL-2 I/O interface
z 66 pin TSOPII and 60 ball BGA package
Ordering Information
PRODUCT NO.
MAX FREQ
M13S128168A -4TG
M13S128168A -5TG
M13S128168A -6TG
M13S128168A -4BG
M13S128168A -5BG
M13S128168A -6BG
250MHz
200MHz
166MHz
250MHz
200MHz
166MHz
VDD
2.7V
2.5V
2.7V
2.5V
PACKAGE
TSOPII
BGA
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
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