M13S128168A_08 Datasheet, PDF (48/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Revision History
Revision
0.1
0.2
0.3
0.4
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
M13S128168A
Date
2002.01.15
2002.11.19
2003.08.08
2003.08.27
2003.10.21
2003.11.10
2004.01.12
2004.03.12
2005.06.23
2006.05.29
2007.01.03
2007.04.12
2007.06.01
2008.02.21
2008.08.18
2008.09.12
2008.12.23
Description
Original
changed ordering information & DC/AC characteristics
Change IDD6 from 3mA to 5mA
Changed ordering information & DC/AC characteristics
Modify tWTR from 2tck to 1tck
1. Correct some refresh interval that is not revised.
2. Correct some CAS Latency that is not revised.
1. Correct IDD1; IDD4R and IDD4W test condition.
2. Correct tRCD; tRP unit
3. Add tCCD spec.
4. Add tDAL spec.
Add CAS Latency=2; 2.5
1. Add Pb-free to ordering information
2. Modify IDD0 and IDD1 spec
3. Modify some AC timing unit from tCK to ns.
1. Delete CL2 ; CL2.5
2. Modify tREFI
3. Delete Non-pb-free form ordering information
Add CL2.5
Add BGA package
Delete CL 2.5
1. Modify 66-Lead TSOP(II) packing dimension
2. Modify Power-up & Initialization Sequence
1. Move Revision History to the last
2. Modify tRCD from 18ns to 15ns
1. Modify the test condition of IDD4
2. Modify t_RP, t_WR,and t_WTR
1. Add -4 speed grade
2. Modify the specification of I_I, IDD0, IDD2N and IDD3N
3. Modify the description about self fresh operation
4. Correct typo error
5. Add the specification of t_QHS
6. Modify t_RAS(max)
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
48/49