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M13S128168A_08 Datasheet, PDF (6/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
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ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (VREF)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
Input timing measurement reference level
Output timing reference level
M13S128168A
Value
0.5*VDDQ
1.5
1.0
VREF+0.31/VREF-0.31
VREF
VTT
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(VDD = 2.375V~2.75V, VDDQ=2.375V~2.75V, TA =0 °C to 70 °C )
(VDD = 2.6V~2.8V, VDDQ=2.6V~2.8V, TA =0 °C to 70 °C (for speed -4))
Parameter
Symbol
-4
Min
Max
Clock Period
CL3
tCK
4.0
10
Access time from CLK/ CLK
tAC
-0.75
+0.75
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each
input)
tCH
tCL
tDQSCK
tDQSS
tDS
tDH
tDIPW
0.45
0.45
-0.6
0.9
0.6
0.5
1.75
0.55
0.55
+0.6
1.1
-
-
-
Input setup time (fast slew rate)
tIS
0.75
-
Input hold time (fast slew rate)
tIH
0.75
-
Input setup time (slow slew rate)
tIS
0.8
-
Input hold time (slow slew rate)
tIH
0.8
-
Control and Address input pulse width
tIPW
2.2
-
DQS input high pulse width
tDQSH
0.4
-
DQS input low pulse width
tDQSL
0.4
-
DQS falling edge to CLK rising-setup
time
tDSS
0.2
-
DQS falling edge from CLK rising-hold
time
tDSH
0.2
-
Data strobe edge to output data edge
tDQSQ
-
0.45
Data-out high-impedance window from
CLK/ CLK
tHZ
-0.7
+0.7
Data-out low-impedance window from
CLK/ CLK
tLZ
-0.7
+0.7
-5
Min
Max
5.0
10
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.75
1.25
0.45
-
0.45
-
1.75
-
0.75
-
0.75
-
0.8
-
0.8
-
2.2
-
0.4
0.6
0.4
0.6
0.2
-
0.2
-
-
0.45
-0.7
+0.7
-0.7
+0.7
-6
Min
Max
6.0
10
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.75
1.25
0.45
-
0.45
-
1.75
-
0.75
-
0.75
-
0.8
-
0.8
-
2.2
-
0.4
0.6
0.4
0.6
0.2
-
0.2
-
-
0.45
-0.7
+0.7
Unit
ns
ns
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
ns
ns
-0.7
+0.7
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
6/49
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