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M13S128168A_08 Datasheet, PDF (4/49 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
◁
ESMT
M13S128168A
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
Power dissipation
Short circuit current
VIN, VOUT
-0.5 ~ 3.6
V
VDD
-1.0 ~ 3.6
V
VDDQ
-0.5 ~ 3.6
V
TSTG
-55 ~ +150
°C
PD
TBD
W
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C )
Parameter
Symbol
Min
-4
-5/6
Max
-4
-5/6
Unit Note
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT)
Output Low Current (Normal strength driver)
(VOUT = 0.373V)
Output High Current (Weak strength driver)
(VOUT =VDDQ-0.763V, min VREF, min VTT)
Output Low Current (Weak strength driver)
(VOUT = 0.763V)
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VID (DC)
II
IOZ
IOH
IOL
IOH
IOL
2.6
2.375
2.8
2.75
V
2.6
2.375
2.8
2.75
V
0.49*VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-0.3
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
V
1
V
2
V
V
V
0.36
VDDQ + 0.6
V
3
-2
2
μA
4
-5
5
μA
-16.8
mA
+16.8
mA
-9
mA
+9
mA
Notes: 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF .
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
4. VIN = 0V to VDD, All other pins are not tested under VIN = 0V.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
4/49
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