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M12L128168A2L Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – ABSOLUTE MAXIMUM RATINGS
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ESMT
M12L128168A (2L)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V， TA = 0 to 70 °C )
Parameter
Value
Input levels (Vih/Vil)
2.4/0.4
Input timing measurement reference level
1.4
Input rise and fall-time
tr/tf = 1/1
Output timing measurement reference level
1.4
Output load condition
See Fig. 2
Output
870 Ω
3.3V
1200 Ω
VOH (DC) =2.4V , IOH = -2 mA
50pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50 Ω
Unit
V
V
ns
V
Vtt = 1.4V
50 Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-5
Row active to row active delay
tRRD(min)
10
RAS to CAS delay
tRCD(min)
15
Row precharge time
tRP(min)
15
Row active time
tRAS(min)
38
tRAS(max)
@ Operating
tRC(min)
53
Row cycle time
@ Auto refresh tRFC(min)
55
Last data in to col. address delay tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Refresh period (4,096 rows)
tREF(max)
Col. address to col. address delay tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
Version
-6
12
18
18
40
100
58
60
1
2
1
64
1
2
1
Unit Note
-7
14
ns
1
20
ns
1
20
ns
1
42
ns
1
us
63
ns
1
70
ns
1,5
CLK
2
CLK
2
CLK
2
ms
6
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.3
5/45
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