M12L128168A2L Datasheet, PDF (1/45 Pages) Elite Semiconductor Memory Technology Inc. – ABSOLUTE MAXIMUM RATINGS

ESMT
SDRAM
FEATURES
y JEDEC standard 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y Burst Read single write operation
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
M12L128168A (2L)
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M12L128168A-5TG2L 200MHz 54 Pin TSOP II Pb-free
M12L128168A-5BG2L 200MHz 54 Ball FBGA Pb-free
M12L128168A-6TG2L 166MHz 54 Pin TSOP II Pb-free
M12L128168A-6BG2L 166MHz 54 Ball FBGA Pb-free
M12L128168A-7TG2L 143MHz 54 Pin TSOP II Pb-free
M12L128168A-7BG2L 143MHz 54 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
BALL CONFIGURATION (TOP VIEW)
(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.3
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