S1D13506 Datasheet, PDF (667/696 Pages) Epson Company – S1D13506 Color LCD/CRT/TV Controller

Epson Research and Development
Vancouver Design Center
Page 9
2.1.2 Access Cycles
Once an address in the appropriate range is placed on the external address bus (A[23:1]),
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the S1D13506 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
SDCLKOUT
A[23:1]
LLBEN,
LUBEN
CSn
IORD,
IOWR
D[15:0]
(write)
D[15:0]
(read)
READY
VALID
VALID
Hi-Z
Hi-Z
VALID
Figure 2-1: NEC V832 Read/Write Cycles
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03