S1D13506 Datasheet, PDF (270/696 Pages) Epson Company – S1D13506 Color LCD/CRT/TV Controller

Page 36
Epson Research and Development
Vancouver Design Center
6.2.2 Power Save Status Bits
REG[1F1h] Power Save Status Register
Memory
n/a
n/a
n/a
n/a
n/a
n/a
LCD Power Controller
Save Status Power Save
Status
The LCD Power Save Status bit is a read-only status bit which indicates the power save
state of the LCD panel. When this bit returns a 1, the panel is powered-off. When this bit
returns a 0, the LCD panel is powered up or in transition of powering up or down. This bit
will return a 1 after a chip reset.
Note
The LCD pixel clock source may be disabled when this bit returns a 1.
REG[1F1h] Power Save Status Register
Memory
n/a
n/a
n/a
n/a
n/a
n/a
LCD Power Controller
Save Status Power Save
Status
The Memory Controller Power Save Status bit is a read-only status bit which indicates the
power save state of the S1D13506 DRAM interface. When this bit returns a 1, the DRAM
interface is powered down (the DRAM is either in self-refresh mode or completely idle).
When this bit returns a 0, the DRAM interface is active. This bit will return a 0 after a chip
reset.
For this bit to return a 1, the DRAM Refresh Select bits must select either self-refresh or no
refresh. For information on the DRAM Refresh Select bits, see Section 6.2.3, “DRAM
Refresh Selection” on page 37.
Note
The memory clock source may be disabled when this bit returns a 1.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06