S1D13506 Datasheet, PDF (631/696 Pages) Epson Company – S1D13506 Color LCD/CRT/TV Controller

Epson Research and Development
Vancouver Design Center
Page 9
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the
TX3912 microprocessor.
The TX3912 Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset, the bus interface signals assume their selected configu-
ration. For details on S1D13506 configuration, see Section 4.2, “S1D13506 Configu-
ration” on page 12.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 TX3912 Host Bus Interface Pin Mapping
The following table shows the function of each Host Bus Interface signal.
Table 3-1: TX3912 Host Bus Interface Pin Mapping
S1D13506
Pin Names
AB20
AB19
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Toshiba TX3912
ALE
CARDREG*
CARDIORD*
CARDIOWR*
V_DD
A[12:0]
D[23:16]
D[31:24]
CARDxCSH*
V_DD
V_DD
DCLKOUT
V_DD
CARDxCSL*
RD*
WE*
CARDxWAIT*
PON*
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02