EN25S64 Datasheet, PDF (36/62 Pages) Eon Silicon Solution Inc. – 64 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

Fast Read Burst (0Dh)
EN25S64
To execute a Fast Read Burst operation the host drivers CS# low, and sends the Read Burst command
cycle (0Dh), followed by three address cycles and three dummy cycles (6 clocks). Each of cycle is
consisted of two nibbles (clocks) long, most significant nibble first,
After the dummy cycle, the device outputs data on the falling edge of the CLK signal starting from the
specific address location. The data output stream is continuous through all addresses until terminated
by a low-to high transition of CS# signal.
During Read Burst, the internal address point automatically increments until the last byte of the burst
reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the bust length,
see Table 10. For example, if the burst length is 8 bytes, and the start address is 06h, the burst
sequence should be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05, 06, etc. The pattern would repeat until the
command was terminated by pulling CS# as high status.
Figure 20. Fast Read Burst Instruction Sequence Diagram ( 0Dh : 3 dummy cycles / 6 clocks )
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. G, Issue Date: 2011/09/23
www.eonssi.com