EN25S64 Datasheet, PDF (13/62 Pages) Eon Silicon Solution Inc. – 64 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

Table 3. Protected Area Sizes Sector Organization
EN25S64
Status Register Content
Memory Content
BP3 BP2
Bit Bit
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Areas
None
Block 0 to 125
Block 0 to 123
Block 0 to 119
Block 0 to 111
Block 0 to 95
Block 0 to 63
All
None
Block 126 to 127
Block 124 to 127
Block 120 to 127
Block 112 to 127
Block 96 to 127
Block 64 to 127
All
Addresses
None
000000h-7DFFFFh
000000h-7BFFFFh
000000h-77FFFFh
000000h-6FFFFFh
000000h-5FFFFFh
000000h-3FFFFFh
000000h-7FFFFFh
None
7E0000h-7FFFFFh
7C0000h-7FFFFFh
780000h-7FFFFFh
700000h-7FFFFFh
600000h-7FFFFFh
400000h-7FFFFFh
000000h-7FFFFFh
Density(KB) Portion
None
8064KB
7936KB
7680KB
7168KB
6144KB
4096KB
8192KB
None
128KB
256KB
512KB
1024KB
2048KB
4096KB
8192KB
None
Lower 126/128
Lower 124/128
Lower 120/128
Lower 112/128
Lower 96/128
Lower 64/128
All
None
Upper 2/128
Upper 4/128
Upper 8/128
Upper 16/128
Upper 32/128
Upper 64/128
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or
Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
13
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. G, Issue Date: 2011/09/23
www.eonssi.com