EN25S64 Datasheet, PDF (31/62 Pages) Eon Silicon Solution Inc. – 64 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

EN25S64
Figure 16.1. Quad Input / Output Fast Read Instruction Sequence under EQPI Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-
bit address interleave on DQ₃, DQ₂, DQ₁ and DQ₀ -> performance enhance toggling bit P[7:0] -> 4
dummy clocks -> data out interleave on DQ₃, DQ₂, DQ₁ and DQ₀ till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown
in Figure 17.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. These
commands will reset the performance enhance mode. And afterwards CS# is raised or issuing FFh
command (CS# goes high -> CS# goes low -> sending FFh -> CS# goes high) instead of no toggling,
the system then will escape from performance enhance mode and return to normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
31
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. G, Issue Date: 2011/09/23
www.eonssi.com