EN25S64 Datasheet, PDF (16/62 Pages) Eon Silicon Solution Inc. – 64 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

EN25S64
7. Two dummy cycles (4 clocks) are necessary for Read Burst with Wrap mode.
8. Three dummy cycles (6 clocks) are necessary for Fast Read Burst with Wrap mode.
Table 6. Manufacturer and Device Identification
OP Code
ABh
90h
9Fh
(M7-M0)
1Ch
1Ch
(ID15-ID0)
3817h
(ID7-ID0)
76h
76h
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the EN25S64 the host drives CS# low, sends the Reset-Enable command (66h), and drives
CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the Reset-
Enable.
A successful command execution will reset the Status register and the Suspend Status register to data
= 00h, see Figure 5 for SPI Mode and Figure 5.1 for Quad Mode. A device reset during an active
Program or Erase operation aborts the operation, which can cause the data of the targeted address
range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery
from a Write operation requires more software latency time ( t_SR) than recovery from other operations.
Figure 5. Reset-Enable and Reset Sequence Diagram
This Data Sheet may be revised by subsequent versions
16
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. G, Issue Date: 2011/09/23
www.eonssi.com