EPVP6300 Datasheet, PDF (20/63 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6300
VFD Controller
7.2.8 R7 (PORT7 Output Data, ADC , Counter1 Data
a) PAGE 0 (PORT7 Output Data Register for HV)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
P77
P76
P75
P74
P73
P72
W-0
W-0
W-0
W-0
W-0
W-0
Bit 1
P71
W-0
Bit 0
P70
W-0
b) PAGE 1 (ADC Control Bit)
Bit 7
Bit 6
Bit 5
Bit 4
IN2
IN1
IN0 ADCLK1
R/W-0 R/W-0 R/W-0 R/W-0
Bit 3
ADCLK0
R/W-0
Bit 2
ADPWR
R/W-0
Bit 1
ADRES
R/W-0
Bit 0
ADST
R/W-0
Bit 0(ADST) : AD converter start to sample
By setting to “1,” the AD will start to sample the data. This bit is automatically
cleared by hardware after a sampling.
Bit 1(ADRES) : Resolution selection for ADC
0 ADC is an 8-bit resolution
When 8-bit resolution is selected, the most significant (MSB) 8-bit data output
of the internal 10-bit ADC will be mapped to RA PAGE1. Therefore, R5
PAGE1 Bit 6 ~ 7 will be of no use.
1 ADC is 10-bit resolution
When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC
will be exactly mapped to RA PAGE1 and R5 PAGE1 Bit 6 ~7.
Bit 2(ADPWR) : AD converter power control, 1/0 enable/disable
Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit ‘s sampling clock source.
For PLL Clock = 895.658kHz ~ 17.9MHz (CLK2~CLK0 = 001 ~ 110)
ADCLK1 ADCLK0 Sampling Rate Operation Voltage
0
0
74.6K
>=3.5V
0
1
37.4K
>=3.0V
1
0
18.7K
>=2.5V
1
1
9.3K
>=2.5V
For PLL Clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1 ADCLK0 Sampling rate Operation voltage
0
0
37.4K
>=3.0V
0
1
18.7K
>=3.0V
1
0
9.3K
>=2.5V
1
1
4.7K
>=2.5V
14 of 63 11.04.2004 (V1.92)
This specification is subject to change without further notice.