EPVP6300 Datasheet, PDF (16/63 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6300
VFD Controller
"TBL" allows a relative address to be added to the current PC, and the contents of the ninth
and tenth bits do not change. The most significant bit (A10~A13) will be loaded with the
contents of bit PS0~PS3 in the status register (R5 PAGE 1) upon execution of a "JMP,”
"CALL,” "ADD R2, A.” or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at Page0. The CPU will
automatically store ACC, R3 status, and R5 PAGE 1, and they will be restored after execution
of instruction RETI.
7.2.4 R3 (Status, Page Selection)
(Status Flag, Page Selection Bits)
Bit 7
Bit 6
Bit 5
Bit 4
RPAGE1 RPAGE0 IOCPAGE
T
R/W-0 R/W-0 R/W-0
R
Bit 3
P
R
Bit 2
Z
R/W
Bit 1
DC
R/W
Bit 0
C
R/W
Bit 0 (C) : Carry flag
The carry flag is affected by following operation :
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will
be "1", in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a
borrow-in, the CF will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision : CF is as a borrow-in indicator for Comparision operation as the same as
subtraction
operation.
d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out
data after rotation.
Bit 1 (DC) : Auxiliary carry flag
Bit 2 (Z) : Zero flag
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be
"1", otherwise, the ZF will be "0".
Bit 3 (P) :
Bit 4 (T) :
Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"
command.
Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0
by WDT timeout.
10 of 63 11.04.2004 (V1.92)
This specification is subject to change without further notice.