HB54A5128FN-A75B Datasheet, PDF (8/17 Pages) Elpida Memory – 512MB Unbuffered DDR SDRAM DIMM

HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These
SPD are based on JEDEC Committee Ballot JC-42.5-99-129.
2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII
code.)
3. Bytes 95 through 98 are assembly serial number.
4. All bits of 99 through 127 are not defined (“1” or “0”).
5. These specifications are defined based on component specification, not module.
Block Diagram (HB54A5128FN)
/S0
RS
DQS0
8 RS
E DQ0toDQ7
RS
DQS1
8 RS
DQ8 to DQ15
RS
O DQS2
8 RS
DQ16 to DQ23
RS
DQS3
8 RS
LDQ24 to DQ31
RS
DQS4
8 RS
DQ32 to DQ39
RS
DQS5
P8 R_S
DQ40 to DQ47
RS
DQS6
8 RS
DQ48 to DQ55
r_RS
DQS7
8 RS
o _{DQ56 to DQ63}
DQS /CS DM
DQ D0
DQS /CS DM
DQ D1
DQS /CS DM
DQ D2
DQS /CS DM
DQ D3
DQS /CS DM
DQ D4
DQS /CS DM
DQ D5
DQS /CS DM
DQ D6
DQS /CS DM
DQ D7
DQS /CS DM
DQ D8
DQS /CS DM
DQ D9
DQS /CS DM
DQ D10
DQS /CS DM
DQ D11
DQS /CS DM
DQ D12
DQS /CS DM
DQ D13
DQS /CS DM
DQ D14
DQS /CS DM
DQ D15
/S1
RS
DM0/DQS9
RS
DM1/DQS10
RS
DM2/DQS11
RS
DM3/DQS12
RS
DM4/DQS13
RS
DM5/DQS14
RS
DM6/DQS15
RS
DM7/DQS16
* D0 to D15: HM5425801
U0: 2k bits EEPROM
d ^{RS: 22Ω}
VCC, VCCQ
VREF
VSS
u ^VCCID
open
D0 to D15
D0 to D15
D0 to D15
Clock wiring
Clock input DDR SDRAMS
CK0/ /CK0 4DRAM loads
c CK1/ /CK1 6DRAM loads
CK2/ /CK2 6DRAM loads
t ^{Note: Wire per Clock loading table/Wiring diagrams.}
A0 to A12
BA0, BA1
/RAS
/CAS
/WE
CKE0
CKE1
A0 to A12 (D0 to D15)
BA0, BA1 (D0 to D15)
/RAS (D0 to D15)
/CAS (D0 to D15)
/WE (D0 to D15)
CKE (D0 to D7)
CKE (D8 to D15)
Serial PD
SCL
SCL
SDA
SDA
U0
A0 A1 A2
SA0 SA1 SA2
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
Data Sheet E0087H40 (Ver. 4.0)
8