HB54A5128FN-A75B Datasheet, PDF (14/17 Pages) Elpida Memory – 512MB Unbuffered DDR SDRAM DIMM

HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
[HB54A5128FN]
Parameter
Symbol
Pins
min.
max.
Unit
Notes
Input capacitance
CI1
Address, Cont.

110
pF
1
Input capacitance
CI2
CKE, /S

75
pF
1
Input capacitance
CI3
CK, /CK

79
Data and DQS input/output
capacitance
CO
DQ, DQS

20
pF
1, 2
[HB54A5129FN]
Parameter
Symbol
Pins
min.
max.
Unit
Notes
E_{Input capacitance}
CI1
Address, Cont.

117
pF
1
Input capacitance
CI2
CKE, /S

82
pF
1
Input capacitance
CI3
CK, /CK

79
Data and DQS input/output
O_capacitance
CO
DQ, DQS, CB

20
pF
1, 2
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
L ^{Timing Parameter Measured in Clock Cycle for Unbuffered DIMM}
Parameter
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
P ^{Write to read command delay (to input all data)}
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
r _{(CL = 2)}
(CL = 2.5)
o Read command to write command delay (to output all data)
(CL = 2)
(CL = 2.5)
Pre-charge command to High-Z
d (CL = 2)
(CL = 2.5)
Write command to data in latency
Write recovery
u _{DM to data in latency}
Register set command to active or register set command
Self refresh exit to non-read command
c _{Self refresh exit to read command}
Power down entry
t ^{Power down exit to command input}
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
tWR
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
Number of clock cycle
min.
max.
3 + BL/2
BL/2
2 + BL/2
2
3
2
2.5
2 + BL/2
3 + BL/2
2
2.5
1
2
0
2
10
200
1
1
CKE minimum pulse width
tCKEPW
1
Data Sheet E0087H40 (Ver. 4.0)
14