HB54A5128FN-A75B Datasheet, PDF (6/17 Pages) Elpida Memory – 512MB Unbuffered DDR SDRAM DIMM

HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
20ns
28
Minimum row active to row active
delay (tRRD)
0
29
Minimum /RAS to /CAS delay (tRCD) 0
Minimum active to precharge time
30
(tRAS)
0
-A75B/B75B
-10B
0
E₃₁
Module bank density
0
Address and command setup time
32
before clock (tIS)
1
-A75B/B75B
O_-10B
1
Address and command hold time after
33
clock (tIH)
1
-A75B/B75B
L^-10B
1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
3C
50
2D
32
40
90
B0
90
B0
15ns
20ns
45ns
50ns
2 banks
256MB
0.9ns*⁵
1.1ns*⁵
0.9ns*⁵
1.1ns*⁵
34
35
36 to 40
41
42
43
44
45
46 to 61
62
Data input setup time before clock
(tDS)
-A75B/B75B
0 1 0 1 0 0 0 0 50
-10B
0 1 1 0 0 0 0 0 60
Data input hold time after clock (tDH)
-A75B/B75B
0
1
0
1
0
0
0
0
50
P -10B
0 1 1 0 0 0 0 0 60
Superset information
0 0 0 0 0 0 0 0 00
Active command period (tRC)
-A75B/B75B
0 1 0 0 0 0 0 1 41
r ^-10B
0 1 0 0 0 1 1 0 46
Auto refresh to active/
Auto refresh command cycle (tRFC) 0 1 0 0 1 0 1 1 4B
o _-A75B/B75B
-10B
0 1 0 1 0 0 0 0 50
SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30
Dout to DQS skew
d _-A75B/B75B
0 0 1 1 0 0 1 0 32
-10B
0 0 1 1 1 1 0 0 3C
Data hold skew (tQHS)
-A75B/B75B
0 1 1 1 0 1 0 1 75
u _-10B
1 0 1 0 0 0 0 0 A0
Superset information
0 0 0 0 0 0 0 0 00
ct ^{SPD revision}
0 0 0 0 0 0 0 0 00
0.5ns*⁵
0.6ns*⁵
0.5ns*⁵
0.6ns*⁵
Future use
65ns*⁵
70ns*⁵
75ns*⁵
80ns*⁵
12ns*⁵
500ps*⁵
600ps*⁵
750ps*⁵
1000ps*⁵
Future use
Initial
Data Sheet E0087H40 (Ver. 4.0)
6