EDX5116ACSE Datasheet, PDF (52/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

EDX5116ACSE
Write Masking
D1[0][7:0]
Figure 41 shows the logic used by the XDR DRAM device
The eight bits of each byte is compared to the value in the byte
when a write-masked command (WRM) is specified in a
mask field (M[7:0]). If they are not equal (NE), then the corre-
COLM packet. This masking logic permits individual bytes of a ^{sponding write enable signal (WE) is asserted and the byte is}
write data packet to be written or not written according to the ^{written into the sense amplifier. If they are equal, then the cor-}
value of an eight bit write mask M[7:0].
responding write enable signal (WE) is deasserted and the byte
In Figure 41, there are 16 sets of 16 bit signals forming the
D1[15:0][15:0] input bus for the Byte Mask block. These are
treated as 2x16 8-bit bytes:
D1[15][15:8]
D1[15][7:0]
...
ED1[1][15:8]
D1[1][7:0]
D1[0][15:8]
OFigure 41 Byte Mask Logic
S[15][15:8]
L⁸
S[15][7:0]
WE-MSB
[15]
18
NE
WE-LSB
[15]
1
NE
8
Compare ₈
Compare
88
88
M[7:0]
D1[15][15:8]
D1[15][7:0]
P ₈
D1[15][15:8]
8
D1[15][7:0]
is not written into the sense amplifier.
In the example of Figure 41, a WRM command performs a
masked write of a 64 byte data packet to all the memory
devices connected to the RQ bus (and receiving the com-
mand). It is the job of the memory controller to search the 64
bytes to find an eight bit data value that is not used and place it
into the M[7:0] field. This will always be possible because there
are 256 possible 8-bit values and there are only 64 possible val-
ues used in the bytes in the data packet.
S[0][15:8]
WE-MSB
[0]
8
1
NE
S[0][7:0]
WE-LSB
[0]
8
1
NE
8
Compare ₈
Compare
88
88
D1[0][15:8]
D1[0][7:0]
8
D1[0][15:8]
8
D1[0][7:0]
rod ₈
u M[7:0]
4+3
WIDTH[2:0]
ct ^SC[3:0]
S[15:0][15:0]
16x16
16x16
Byte Mask (WR)
16x16
D1[15:0][15:0]
Dynamic Width Demux (WR)
16x16
Dynamic Width Mux (RD)
16x16
4+3
WIDTH[2:0]
SC[3:0]
D[15:0][15:0]
Q[15:0][15:0]
Note that other systems might use a data transfer size that is
different than the 64 bytes per t_CC interval per RQ bus that is
used in the example in Figure 41.
Figure 42 shows the timing of two successive WRM com-
mands in COLM packets. The timing is identical to that of two
successive WR commands in COL packets. The one difference
Preliminary Data Sheet E0881E20 (Ver. 2.0)
52