EDX5116ACSE Datasheet, PDF (30/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

EDX5116ACSE
As a result of these propagation delays, the position of packets by evaluating the two timing paths between cycle T₉ at the
will have timing skews that depend upon whether they are
Controller and cycle T₂₁at the XDR DRAM:
measured at the pins of the memory controller or the pins of
t_∆RW + t_PD-RQ+ t_CWD =
the memory component. For example, the CFM/CFMN sig-
nals at the pins of the memory component are t_PD-RQ later
than at the pins of the memory controller. This is shown by the
t_PD-RQ+ t_CAC + t_CC+ t_{RW-BUB,XDRDRAM}
or
cycle numbering of the CFM/CFMN signals at the two loca-
t_∆RW= (t_CAC - t_CWD)+ t_CC + t_{RW-BUB,XDRDRAM}
tions — in this example cycle T₁ at the memory controller
aligns with cycle T₀ at the memory component.
All the request packets on the RQ wires will have a t_PD-RQ
skew at the memory component relative to the memory con-
troller in this example. Because the t_PD-D propagation delay of
E^{write data matches the t}PD-RQ ^{propagation delay of the write}
command, the controller may issue the write data packet D(a0)
relative to the COL packet with the first write command “WR
a0” with the normal write data delay t_CWD. If the propagation
O ^{delays between the memory controller and memory compo-}
nent were different for the RQ and DQ buses (not shown in
this example), the write data delay at the memory controller
would need to be adjusted.
L ^{A propagation delay is seen by the read command — that is,}
The following relationship was shown for Figure 12
t_{∆RW ,MIN}= (t_CAC - t_CWD)+ t_CC + t_{RW-BUB,XDRDRAM,MIN}
or
(t_∆RW - t_{∆RW ,MIN})=
(t_{RW-BUB,XDRDRAM} - t_{RWBUB,XDRDRAM,MIN})
In other words, the two timing parameters t_{RW-BUB,XDRDRAM}
and t_∆RW will change together. The relationship of this change
to the propagation delay t_PD,CYC (= t_PD-D+t_PD-Q) can be
derived by looking at the two timing paths from T15 to T21 at
the XDR DRAM:
t_PD-Q + t_CC + t_RW-BUB,XIO+ t_PD-D =
t_CC+ t_{RW-BUB,XDRDRAM}
the read command will be delayed by a t_PD-RQ skew at the
memory component relative to the memory controller. The
memory component will return the read data packet Q(b0) rel-
ative to this read command with the normal read data delay
t_CAC (at the pins of the memory component).
P The read data packet will be skewed by an additional propaga-
tion delay of t_PD-Q as it travels from the memory component
back to the memory controller. The effective read data delay
measured between the read command and the read data at the
r ^{memory controller will be t}CAC ^+tPD-RQ^+tPD-Q^.
The t_PD-RQ factor is caused by the propagation delay of the
o ^{request packets as they travel from memory controller to mem-}
ory component. The t_PD-Q factor is caused by the propagation
delay of the read data packets as they travel from memory com-
ponent to memory controller.
d _{All timing parameters will be equal to their minimum values}
except t_{WR-BUB,XDRDRAM} (as in the top diagram), and the tim-
ing parameters t_{RW-BUB,XDRDRAM} and t_∆RW. These will be
u ^{larger than their minimum values by the amount (tPD,CYC-}
ct ^{tPD,CYC,MIN), where tPD,CYC = tPD-D+tPD-Q. This may be seen}
or
t_{RW-BUB,XDRDRAM} = t_RW-BUB,XIO + t_PD-D + t_PD-Q
or
t_{RW-BUB,XDRDRAM} = t_RW-BUB,XIO + t_PD,CYC
in a system with minimum propagation delays:
t_{RW-BUB,XDRDRAM,MIN} = t_RW-BUB,XIO + t_PD,CYC,MIN
and since t_RW-BUB,XIO is equal to t_{RW-BUB,XIO,MIN} in both
cases, the following is true:
(t_PD,CYC - t_PD,CYC,MIN) =
(t_{RW-BUB,XDRDRAM} - t_{RW-BUB,XDRDRAM,MIN}) =
(t_∆RW - t_{∆RW ,MIN})=
In other words, the values of the t_{RW-BUB,XDRDRAM,MIN} and
t_{∆RW ,MIN} timing parameters correspond to the value of
t_PD,CYC,MIN for the system (this is equal to one t_CYCLE). As
t_PD,CYC is increased from this minimum value, t_RW-
BUB,XDRDRAM ^{and t}∆RW ^{increase from their minimum values}
by an equivalent amount.
Preliminary Data Sheet E0881E20 (Ver. 2.0)
30