EDX5116ACSE Datasheet, PDF (46/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

EDX5116ACSE
Initialization
to VTERM. The SDO output of each XDR DRAM device is
transmitted to the SDI input of the next XDR DRAM device
Figure 37 shows the topology of the serial interface signals of a _{(in the direction of the controller). This SDO/SDI daisy-chain}
XDR DRAM system. The three signals RST, CMD, and SCK _{topology continues to the controller, where it ends at the SRD}
are transmitted by the controller and are received by each XDR _{input of the controller. All the serial interface signals are low-}
DRAM device along the bus. The signals are terminated to the _{true. All the signals use RSL signaling circuits, except for the}
VTERM supply through termination components at the end
SDO output which uses CMOS signaling circuits.
farthest from the controller. The SDI input of the XDR
DRAM device furthest from the controller is also terminated
Figure 37 Serial Interface System Topology
E_{RST CMD SCK}
O _{... SRD}
L ^Controller
RST CMD SCK
SDO
SDI
XDR DRAM
RST CMD SCK
SDO
SDI
XDR DRAM
...
VTERM
RST CMD SCK
SDO
SDI
XDR DRAM
Figure 38 shows the initialization timing of the serial interface
for the XDR DRAM[k] device in the system shown above.
Prior to initialization, the RST is held at zero. The CMD input
is not used here, and should also be held at zero. Note that the
P _{inputs are all sampled by the negative edge of the SCK clock}
input. The SDI input for the XDR DRAM[0] device is zero,
and is unknown for the remaining devices.
r ^{Figure 38 Initialization Timing for XDR DRAM[k] Device}
On negative SCK edge S₈ the RST input is sampled one. It is
sampled one on the next four edges, and is sampled zero on
edge S₁₂ a time t_RST-10 after it was first sampled one. The state
of the control registers in the XDR DRAM device are set to
their reset values after the first edge (S₈) in which RST is sam-
pled one.
o ^Poweron
0
SCK
1
0
d RST
1
0
CMD
1
u ⁰
SDI
(input) ₁
0
SDO
ct ^{(output) 1}
t_COREINIT
S₀ S₂ S₄ S₆ S₈ S₁₀ S₁₂ S₁₄ S₁₆ S₁₈ S₂₀ S₂₂ S₂₄ S₂₆ S₂₈ S₃₀ S₃₂ S₃₄ S₃₆ S₃₈ S
t_RST-SCK
t_RST-10
t_CYC,SCK
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
t_RST-SDI,00 = k * t_CYC,SCK
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
t_RST-SDO,11
t_SDI-SDO,00
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
The SDI inputs will be sampled one within a time t_RST-SDO,11
after RST is first sampled one in all the XDR DRAMs except
for XDR DRAM[0]. XDR DRAM[0]’s SDI input will always
be sampled zero.
XDR DRAM[k] will see its RST input sampled zero at S₁₂, and
will then see its SDI input sampled zero at S₁₆ (after SDI had
Preliminary Data Sheet E0881E20 (Ver. 2.0)
46