EDX5116ACSE Datasheet, PDF (1/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

PRELIMINARY DATA SHEET
512M bits XDR^ DRAM
EDX5116ACSE (32M words × 16 bits)
Overview
• Low power
The EDX5116ACSE is a 512M bits XDR^™ DRAM organized
as 32M words × 16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
E_{nology permits 4000/3200 Mb/s transfer rates while using}
Pin Configuration _{conventional system and board design technologies. XDR}
DRAM devices are capable of sustained data transfers of
8000/6400 MB/s.
O_{XDR DRAM device architecture allows the highest sustained}
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
L _{It is packaged in 104-ball FBGA compatible with Rambus}
XDR DRAM pin configuration.
Features P • Highest pin bandwidth available
4000/3200 Mb/s Octal Data Rate (ODR) Signaling
• Bi-directional differential RSL (DRSL)
r ^{- Flexible read/write bandwidth allocation}
- Minimum pin count
• On-chip termination
o _{-Adaptive impedance matching}
-Reduced system cost and routing complexity
• Highest sustained bandwidth per DRAM device
d ^{• 8000/6400 MB/s sustained data rate}
• Eight banks: bank-interleaved transactions at full
bandwidth
• Dynamic request scheduling
u ^{• Early-read-after-write support for maximum efficiency}
• Zero overhead refresh
• Dynamic width control
•EDX5116ACSE supports × 16, × 8 and × 4 mode
c • Low latency
• 2.0/2.5 ns request packets
t ^{• Point-to-point data interconnect for fastest possible}
• 1.8V Vdd
• Programmable small-swing I/O signaling (DRSL)
• Low power PLL/DLL design
• Powerdown self-refresh support
• Per pin I/O powerdown for narrow-width operation
L
KJ H G F
1
DQN3 DQN9 VDD GND VDD Row
2
1234
DQ3 DQ9 VDD
P 3 _{DQN15 DQDNQ55 VDDDQN5RQ10 CFM}
N 4 _{DQ15 DGQN5D GNDVDDRQ11 CFMN}
M 5 _{VDD VDDQD1 VTEDRQMN1}
VDD
6
L
GND
GGNNDD
RQ10GND _{GND GND}
7
K
VDD RQ8
8
J
VDD RQ6
9
H
VREF RQ4
10
G
GND RQ2
11 F _{GND VTEVRDMD}
RQ0 _{GND VDD}
E 12 _VDD
GND RST
GND GND
D 13
DQN7
SD0
DQN13
VDDCMDRQ9
RQ7
C 14
DQ7
DQ0
DQ13
CMDDQN0RQ8
RQ6
B 15 _{DQN11 DQGNN1D SCKVDD}
A 16 _{DQ11 DQD1Q4 GNDDQN4VDD VDD}
GND
VDD
E
GND
5
RSRV
RSRV
VDD
GND
VREF
RQ5
GND
D
CB
A
VDD SDI DQN8 DQN2
67
GND DQ8 DQ2
RDQQ4N7 RQD0Q7 DQN4 DQN14
VRTQE3RM _{GNGDND DQ4 DQ14}
DQN3 _{VTEDRQM3 VDD VDD}
VRDQD11 ^GND GND GND
RQ9 VDD
RQ7 GND
CFMN CFM
RQ5 GND
VRDQD3
VDDVTERM _GND
RQ1 GND
GND GND VDD
SCK SD1
RQ1 VDD DQN12 DQN6
DQN2 DG2
RQ2 GND DQ12 DQ6
VTERM _{RSGTNDDQN0 DQN10}
VDDQDN6 SDDOQ6 DQ0 DQ10
A16
A8
Top view of package
flight time
• Support for low-latency, fast-cycle cores
Doc. No. E0881E20 (Ver. 2.0)
Date Published June 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2008.
Elpida Memory, Inc. 2006