EDX5116ACSE Datasheet, PDF (36/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

EDX5116ACSE
Figure 21 RQ Scan High (RQH) Register
7
6
5
4
3
2
1
0
reserved
RQH[3:0]
RQ Scan High Register
SADR[7:0]: 00000110₂
Read/write register
RQH[7:0] resets to 00000000₂
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
Figure 22 RQ Scan Low (RQL) Register
E₇
6
5
4
3
2
1
OL^RQL[7:0]
0
RQ Scan Low Register
SADR[7:0]: 00000111₂
Read/write register
RQL[7:0] resets to 00000000₂
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
Figure 23 Refresh Bank (REFB) Control Register
7
6
Product ^MBR[1:0]
5
4
3
reserved
2
1
0
BANK[2:0]
Refresh Bank Control Register
Read/write register
SADR[7:0]: 00001000₂
REFB[7:0] resets to 00000000₂
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh oper-
ation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
00₂ - Single-bank refresh.
01₂ - Reserved
10₂ - Reserved
11₂ - Reserved
Preliminary Data Sheet E0881E20 (Ver. 2.0)
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