HB54A1288KM Datasheet, PDF (5/16 Pages) Elpida Memory – 128MB DDR SDRAM S.O. DIMM

HB54A1288KM
Serial PD Matrix*¹
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
128
256 byte
2
Memory type
0
3
Number of row address
0
4
Number of column address
0
5
Number of DIMM banks
0
6
Module data width
0
E7
Module data width continuation
0
8
Voltage interface level of this assembly 0
9
DDR SDRAM cycle time, CL = X
-A75B
0
O^-B75B
0
-10B
1
10
SDRAM access from clock (tAC)
-A75B/B75B
0
L^-10B
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
07
0D
09
01
40
00
04
70
75
80
70
80
SDRAM DDR
13
9
1
64 bits
0 (+)
SSTL 2.5V
CL = 2.5*⁵
0.7ns*⁵
0.8ns*⁵
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DIMM configuration type
0 0 0 0 0 0 0 0 00
Refresh rate/type
1 0 0 0 0 0 1 0 82
Primary SDRAM width
0 0 0 1 0 0 0 0 10
Error checking SDRAM width
0 0 0 0 0 0 0 0 00
P ^{SDRAM device attributes:}
Minimum clock delay back-to-back
column access
0 0 0 0 0 0 0 1 01
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
r ^{SDRAM device attributes: Number of}
banks on SDRAM device
0
0
0
0
0
1
0
0
04
SDRAM device attributes:
o /CAS latency
SDRAM device attributes:
/CS latency
0 0 0 0 1 1 0 0 0C
0 0 0 0 0 0 0 1 01
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02
d _{SDRAM module attributes}
0 0 1 0 0 0 0 0 20
SDRAM device attributes: General 0 0 0 0 0 0 0 0 00
Minimum clock cycle time at
u CLX - 1
-A75B
0 1 1 1 0 1 0 1 75
-B75B/10B
1 0 1 0 0 0 0 0 A0
Maximum data access time (tAC) from
c ^{clock at CLX - 1}
0 1 1 1 0 0 0 0 70
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
Minimum clock cycle time at
t CLX - 1
0 0 0 0 0 0 0 0 00
Non-parity
7.8 µs
Self refresh
× 16
Not used
1 CLK
2, 4, 8
4
2/2.5
0
1
Unbuffered
± 0.2V
CL = 2*⁵
0.7ns*⁵
0.8ns*⁵
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
20ns
Preliminary Data Sheet E0190H10 (Ver. 1.0)
5