HB54A1288KM Datasheet, PDF (13/16 Pages) Elpida Memory – 128MB DDR SDRAM S.O. DIMM

HB54A1288KM
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE 48
pF
1, 3
Input capacitance
CI2
CK, /CK, /S, CKE
40
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
22
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
Timing Parameter Measured in Clock Cycle for Registered DIMM
EParameter
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
O_{Write to read command delay (to input all data)}
Burst stop command to write command delay
(CL = 2)
L ^{(CL = 2.5)}
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
Number of clock cycle
min.
max.
3 + BL/2
BL/2
2 + BL/2
2
3
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5)
Read command to write command delay (to output all data)
(CL = 2)
(CL = 2.5)
P ^{Pre-charge command to High-Z}
(CL = 2)
(CL = 2.5)
Write command to data in latency
r ^{Write recovery}
DM to data in latency
o ^{Register set command to active or register set command}
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
d _{Power down exit to command input}
uct ^{CKE minimum pulse width}
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
tWR
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
tCKEPW
2
2.5
2 + BL/2
3 + BL/2
2
2.5
1
2
0
2
10
200
1
1
1
Preliminary Data Sheet E0190H10 (Ver. 1.0)
13