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HB54A1288KM Datasheet, PDF (1/16 Pages) Elpida Memory – 128MB DDR SDRAM S.O. DIMM | |||
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PRELIMINARY DATA SHEET
128MB DDR SDRAM S.O. DIMM
HB54A1288KM (16M words à 64 bits, 1 Bank) Description
The HB54A1288KM is a 16M Ã 64 Ã 1 bank Double
Data Rate (DDR) SDRAM Module, mounted 4 pieces
of 256Mbits DDR SDRAM (HM5425161BTT) sealed in
TSOP package and 1 piece of serial EEPROM (2k bits
EEEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
Ostrobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 200-pin socket type package (dual lead
out). Therefore, it makes high density mounting
L possible without surface mount technology. It provides
common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the
Product module board.
Features
⢠200-pin socket type package (dual lead out)
 Outline: 67.6mm (Length) à 31.75mm (Height) Ã
3.80mm (Thickness)
 Lead pitch: 0.6mm
⢠2.5V power supply (VCC/VCCQ)
⢠SSTL-2 interface for all inputs and outputs
⢠Clock frequency: 133MHz/100MHz (max.)
⢠Data inputs and outputs are synchronized with DQS
⢠4 banks can operate simultaneously and
independently (Component)
⢠Burst read/write operation
⢠Programmable burst length: 2, 4, 8
 Burst read stop capability
⢠Programmable burst sequence
 Sequential
 Interleave
⢠Start addressing capability
 Even and Odd
⢠Programmable /CAS latency (CL): 2, 2.5
⢠8192 refresh cycles: 7.8µs (8192/64ms)
⢠2 variations of refresh
 Auto refresh
 Self refresh
Document No. E0190H10 (Ver. 1.0)
Date Published September 2001 (K)
Printed in Japan
URL: http://www.elpida.com
This product became EOL in May, 2004.
C Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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