HB52F328EM-75B Datasheet, PDF (16/19 Pages) Elpida Memory – 256MB Unbuffered SDRAM DIMM

HB52F328EM-75B, HB52F329EM-75B
Pin Functions
CK0, CK2 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising
edge.
/S0, /S2 (input pin): When /S is Low, the command input cycle becomes valid. When /S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
/RE, /CE and /W (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the combination
of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command
cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command
cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge
mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0, BA1 (BA) is precharged.
BA0, BA1 (input pin): BA0, BA1 are bank select signal (BA). The memory array is divided into bank 0, bank 1,
bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is
selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge
is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend
modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the
DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data
is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).
Data Sheet E0184H10 (Ver. 1.0)
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