HB52F328EM-75B Datasheet, PDF (15/19 Pages) Elpida Memory – 256MB Unbuffered SDRAM DIMM

HB52F328EM-75B, HB52F329EM-75B
Relationship Between Frequency and Minimum Latency
Parameter
Frequency (MHz)
tCK (ns)
Active command to column command (same bank)
Symbol
IRCD
CL = 3
133
PC100
Symbol 7.5
3
Active command to active command (same bank)
IRC
9
Active command to precharge command (same bank)
IRAS
6
Precharge command to active command (same bank)
IRP
3
Write recovery or data-in to precharge command (same
bank)
IDPL
Tdpl
2
Active command to active command (different bank)
IRRD
2
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
ISREX Tsrx
1
IAPW Tdal
5
Self refresh exit to command input
ISEC
9
Precharge command to high impedance
IHZP
Troh 3
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
IAPR
1
IEP
–2
Column command to column command
ICCD Tccd 1
Write command to data in latency
IWCD Tdwd 0
DQMB to data in
IDID
Tdqm 0
DQMB to data out
IDOD Tdqz 2
CKE to CK disable
ICLE
Tcke 1
Register set to active command
IRSA
Tmrd 1
/S to command disable
ICDD
0
Power down exit to command input
IPEC
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
CL = 2
100
10
2
7
5
2
2
2
1
4
7
2
1
–1
1
0
0
2
1
1
0
1
Notes
1
= [IRAS + IRP]
1
1
1
1
1
2
= [IDPL + IRP]
= [IRC]
3
Data Sheet E0184H10 (Ver. 1.0)
15